The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a transistor and a method of manufacturing it.
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process vertically introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is vertically doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions with less than 30 nanometer (nm) junction depth. Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally either bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices. Most integrated circuits are fabricated in a CMOS process on a bulk semiconductor substrate.
In bulk semiconductor-type devices, transistors, such as, MOSFETs, are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
Conventional SOI-type devices include an insulative substrate attached to a thin-film semiconductor substrate that contains transistors similar to the MOSFETs described with respect to bulk semiconductor-type devices. The insulative substrate generally includes a buried insulative layer above a lower semiconductor base layer. The transistors on the insulative substrate have superior performance characteristics due to the thin-film nature of the semiconductor substrate and the insulative properties of the buried insulative layer. In a fully depleted (FD) MOSFET, the body thickness is so small that the depletion region has a limited vertical extension, thereby eliminating link effect and lowering hot carrier degradation. The superior performance of SOI devices is manifested in superior short-channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
As the physical gate length of MOS transistors shrinks to dimensions of 50 nm and below, ultra-thin-body MOSFETs fabricated on very thin SOI substrates provide significant architectural advantages. The body thickness of such devices can be below 200 Angstroms (xc3x85) to overcome the short-channel effects (e.g., threshold voltage roll-off and drain induced barrier lowering) which tend to be severe in devices with small dimensions.
Source/drain junction formation is very challenging when forming thin film SOI MOSFETs according to conventional processes. More particularly, it is difficult to form abrupt transitions between the source/drain regions and the channel region. These abrupt transistions or junctions are difficult to form due to the effects of a large thermal budget (high temperature).
Conventional processes utilize a high thermal budget to activate dopants, form silicide regions, etc. The large thermal budget tends to increase dopant diffusion, thereby causing the source region and drain region to merge together or short circuit through the channel region. Therefore, it is desirable to control the abruptness of the junction in the lateral direction.
Thus, there is a need for a transistor with abrupt source and drain junctions. Further, there is a need for a method of manufacturing a transistor that has abrupt source and drain junctions. Further still, there is a need for SOI transistors that have abrupt source/drain junctions. Even further still, there is a need for a process of forming abrupt source/drain junctions in the lateral direction.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing a gate structure between a source location and a drain location on a semiconductor film, providing an angled amorphization implant to the film, and providing a source/drain dopant implant. The method also includes annealing the film.
Another exemplary embodiment relates to a method of manufacturing an ultra large-scale integrated circuit including a plurality of field effect transistors. The method includes steps of: providing at least part of a gate structure on a top surface of a semiconductor substrate; providing a photoresist feature over a portion of a source/drain region; and providing an amorphous region in the semiconductor substrate. The semiconductor substrate includes a first non-amorphous region under the gate and a second non-amorphous region under the photoresist feature. The method further includes steps of: doping the source location and the drain location, and recrystallizing the amorphous region.
Another exemplary embodiment relates to a method of doping a source region or a drain region for a transistor. The transistor includes the gate structure disposed over a channel in a substrate. The source region is heavily doped with dopants of a first conductivity type and the drain region is heavily doped with dopants of the first conductivity type. The method includes amorphizing the substrate at an angle, doping the substrate, and annealing the substrate. Abrupt junctions in the lateral direction for the source region and drain region are formed.